人才介绍

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麦穗冬 Terrence Mak
电话: 020-22912747
E-Mail: sd.mai@giat.ac.cn
地址:广州市南沙区海滨路1121号A栋305
  • 简介

  • 出版物

    个人介绍

    2012年入选“青年千人计划”
    主要研究方向为多核系统、嵌入式计算以及脑机接口
    先后获得UK-EPSRC, TSB, EU-FP7 and 中国国家自然科学基金资助
    获得裘槎基金会奖学金 和 DATE’2011最佳论文奖
    先后发表约60篇期刊和会议论文
    与MIT、帝国理工学院、清华大学、电子科技大学等知名大学以及Intel、Oracle等业界知名公司建立学术合作

    工作经历

    香港中文大学Since 8/2012
    计算机科学与工程系
    助理教授

    英国纽卡斯尔大学Since 3/2010 – 8/2012
    电子与计算机工程系
    讲师(相当于助理教授)

    纽卡斯尔生命医学院神经学研究所
    合作讲师

    美国麻省理工学院Since 8/2011

    哈佛 - 麻省理工学院卫生科学与技术研究中心

    Visiting Scientist (supported by The Royal Society)

    教育经历

    英国帝国理工学院12/2009
    电子与电气工程博士, 由 Peter Cheung教授 和 Wayne Luk教授联合指导
    论文题目: Circuit Design and Analysis for On-Chip Communication Systems

    香港中文大学8/2005
    系统工程专业硕士, 导师 为Kai-Pui Lam教授
    论文题目: High-Performance Reconfigurable Computing for Biomedical Applications

    研究方向

    •多核和嵌入式系统设计(片上网络, FPGA, 片上多核处理器)
    •高性能生物计算系统(网络药理学和药物发现, 生物信息学计算系统)
    •脑机接口 (脑植入式系统, 闭环动态夹紧系统)
    •新兴技术(3-D大规模集成技术, 能量获取电路, 动态可编程网络)

    研究项目

    独立项目: 青年千人计划研究经费RMB 2,800,000, 9/2012
    合作项目: 能量自适应可重构系统建模及控制算法– 中国国家自然科学基金委资助, RMB700,000, 2012年1月
    独 立项目: Networked-Processors for Complex Network-based Drug Discovery – Supported by UK Technology Strategy Board, £130,000, granted since 7/2011
    独立项目: Dynamic Programming Networks for 3-D VLSI System Integration – Supported by Royal Society Research Fund, £4,000, granted since 5/2011
    独立项目:Visiting fellowship for collaboration – Support by HiPEAC, European Research Council, €1500, 5/2011
    独 立项目:Champion of Neurally-Inspired Engineering SIG for UK Neuroinformatic Group – Supported by UK Research Council (EPSRC, BBSRC), £8,000, granted since 4/2011
    独立项目:Real-Time Brain-Machine-Interface Using Many-Core Technologies – Supported by UK Research Council (EPSRC), £46,000, granted since 1/2011
    独立项目:Real-Time Neurophysiological Signal Processing Using Array Processors – Newcastle University Start-Up Grant, £5,000, granted since 7/2010
    合作项目: Next Generation Energy-Harvesting Electronics: Holistic Approach – Supported by UK Research Council (EPSRC), £410, 000, granted since 4/2010

    获奖

    香港中文大学工程学院杰出校友, 2011
    Premier International Conference on Design, Automation and Test in Europe (DATE)最佳论文奖 (与会800余篇论文中唯一获奖论文), 4/2011
    裘槎基金会奖学金, 2005-2008
    美国海军研究办公室神经工程领域杰出贡献奖, 2005



    期刊论文

    • 1.Terrence Mak, Truncation Error Analysis of MTBF Computation for Multi-Latch Synchronisers, Elsevier, Microelectronics Journal, 2011 SCI Index:WOS:000301751000009, IDS Number: 911WD

    • 2.Terrence Mak, Kai-Pui Lam, Peter Y.K. Cheung, Wayne Luk, “Adaptive Routing for Network-on-Chips Using a Dynamic Programming Network”, IEEE Trans. Industrial Electronics, Vol. 58, no. 8, pp. 3701-3716, 2011 SCI Index: WOS:000293685700056, IDS Number: 804WT

    • 3.Terrence Mak, Kai-Pui Lam, H.S. Ng, Guy Rachmuth, Chi-Sang Poon, “A CMOS Current-Mode Dynamic Programming Circuit”, IEEE Trans. Circuits and Systems I, Vol. 57, no. 22, pp. 3112-3123, 2010 SCI Index: WOS: 000285361200010, IDS Number: 695HM

    • 4.Terrence Mak, Pete Sedcole, Peter Y.K. Cheung and Wayne Luk, “Average Interconnections Delay Estimation for On-FPGA Communication Links”, IET Electronics Letters, Vol. 43, No. 17, pp 918-920, 2007 SCI Index: WOS:000249282200009, IDS Number: 207WQ

    • 5.Terrence Mak, G. Rachmuth, K.P. Lam, and C-S. Poon, “A Component-based FPGA Design Framework for Neuronal Ion Channel Dynamics Simulations”, IEEE Trans. Neural Systems & Rehabilitation Engineering, Vol.14, No.4, pp 410-418, 2006 SCI Index: WOS:000249282200009, IDS Number: 207WQ

    • 6.Terrence Mak, K. P. Lam, “Equivalence - Set Genes Partitioning Using an Evolutionary - DP Approach”, IEEE Trans. NanoBioscience, Vol. 4, No. 4, pp 295-300, 2005 SCI Index: WOS:000233757200004 , IDS Number: 990QB

    • 7.Terrence Mak, Chi-Sang Poon (Guest Editors), Special Issue: 3-D VLSI Systems Integration, the Computer Journal, Oxford Journal, 2011

    • 8.Terrence Mak, Raaed Al-Dujaily, Kuan Zhou, Kai-Pui Lam, Chi-Sang Poon, “3-D On-Chip Dynamic Programming Network Using TSV-based Technology”, IEEE Circuits and Systems Magazine, Vol. 11, no. 3, 51-62, 2011

    • 9.Terrence Mak, Pete Sedcole, Peter Y.K. Cheung, Wayne Luk, “Global Communication in FPGAs Using Wave-Pipelined Signalling”, Elsevier, Integration, the VLSI Journal, Vol. 43, No. 2, pp188-201, 2010 EI: 11303669

    • 10.Bo Yu, Terrence Mak, Xiangyu Li, Leslie Smith, Yihe Sun and Chi-Sang Poon, Stream-based Hebbian Eigenfilter for Real-Time Neuronal Spike Discrimination, BioMedical Engineering OnLine, vol. 11, no. 18, 2012 SCI Index:WOS:000304062800001, IDS Number: 942QT

    • 11.Raaed Al-Dujaily, Terrence Mak, Fei Xia, Alex Yakovlev and Maurizio Palesi, Embedded Transitive Closure Networks for Run-Time Deadlock Detection in Networks-on-Chip, IEEE Trans. Distributed and Parallel Systems, 2012 SCI Index:WOS:000304413700004, IDS Number: 947FJ

    • 12.Bo Yu, H. M. Chan, Terrence Mak, Y. Sun, Chi-Sang Poon, On-Chip Systolic Networks for Real-Time Tracking of Neural Correlation Networks, (accepted) IEEE Trans. on Biomedical Engineering

    • 13.Raaed Al-Dujaily, Terrence Mak, Kai-Pui Lam, Fei Xia, Alex Yakovlev, Chi-Sang Poon, Dynamic On-Chip Thermal Optimization for 3D Networks-on-Chip, (accepted) The Computer Journal

    • 14.Bo Yu, Terrence Mak, Xiangyu Li, Fei Xia, Alex Yakovlev, Yihe Sun, Chi-Sang Poon, Real-Time FPGA-Based Multi-Channel Spike Sorting Using Hebbian Eigenfilter, (to appear) IEEE Journal on Emerging and Selected Topics in Circuits and Systems: Brain-Machine Interface, 2012

    • 15.Ghaith Tarawneh, Terrence Mak, Alex Yakovlev, Computational Models for Metastability Failure Rates in ADCs, (under review) IEEE Trans. Circuits and Systems I

    • 16.Raaed Al-Dujaily, Terrence Mak, Kai-Pui Lam, Chi-Sang Poon, Dynamic Thermal Optimization in 3-D Networks-on-Chip, (under review) The Computer Journal

    • 17.Nizar Dehir, Terrence Mak, Alex Yakovlev, Modelling and Tools for Power Supply Variation in Networks-on-Chip, (under review) IEEE Trans Computers: Special Issue on Networks-on-Chip

    • 18.Qiang Liu, Terrence Mak, Wayne Luk, A Dual-Step Optimization for Power Adaptive Computing System Design in Energy Harvesting Systems, (under review) IEEE Trans. Industrial Electronics

    • 19.Terrence Mak, Pete Sedcole, Peter Cheung, Wayne Luk, A Stochastic Model for FPGA-Based Communication Link Bandwidth Prediction, (under review) Elsevier, Integration – the VLSI Journal, 2011


    • 会议论文

    • 1.Nizar Dahir, Terrence Mak and Alex Yakovlev, Communication Centric On-Chip Power Grid Models for Networks-On-Chip, VLSI-SoC, Hong Kong, 2011; EI: 20115114621958

    • 2.Kai Lam, Terrence Mak and Chi-Sang Poon, Comparative ODE benchmarking of unidirectional and bidirectional DP networks for 3D-IC, (Invited paper) VLSI-SoC, Hong Kong, 2011; EI: 20115114621946

    • 3.Kai Lam, Terrence Mak and Chi-Sang Poon, Cycle avoidance in 2D/3D bidirectional graphs using shortest-path dynamic programming network, VLSI-SoC, 2011; EI: 20115114621894

    • 4.Terrence Mak, Chi-Sang Poon, Frontier in 3D Integrated Engineering, Special Session, VLSI-SoC, 2011 EI:

    • 5.Bo Yu, Terrence Mak, Chi-Sang Poon, Real-Time Neuronal Networks Reconstruction Using Hierarchical Systolic Arrays, Engineering in Medicine and Biology Conference (EMBC), 2011 ; EI: 20115214634984

    • 6.Bo Yu, Terrence Mak, Leslie Smith, Chi-Sang Poon, Memory Efficient On-Line Streaming for Multichannel Spike Train Analysis, Engineering in Medicine and Biology Conference (EMBC), 2011 ; EI:20115214633935

    • 7.Bo Yu, Terrence Mak, Kenneth Tong, Feasibility Study for Future Implantable Neural-Silicon Interface Device, Engineering in Medicine and Biology Conference (EMBC), 2011; EI:20115214634112

    • 8.Ryan Luo, Terrence Mak, Bo Yu, Peter Andras, Towards Neuro-Silicon Interface Using Reconfigurable Dyanmic Clamping, Engineering in Medicine and Biology Conference (EMBC), 2011

    • 9.Qiang Liu, Terrence Mak, Junwen Luo, Wayne Luk, Aex Yakovlev, Power Adaptive Computing System Design in Energy Harvesting Environment, SAMOS, pp. 1-8, 2011 ; EI:20114514488327

    • 10.Joe Y. Zhou, Terrence Mak, Alex Yakovlev, Run-Time Concurrency Tuning for Peak Power Modulation in Energy Harvesting Systems, ACSD, pp. 1-8, 2011; EI: 20113714329049

    • 11.Terrence Mak, Raaed Al-Dujaily, Kuan Zhou, Kai-Pui Lam, Chi-Sang Poon, 3D Networks-on-Chip, GOMACTech, (Invited paper) Orlando, 2011; EI: 20113714329049

    • 12.Terrence Mak, Raaed Al-Dujaily, Kuan Zhou, Kai-Pui Lam, Chi-Sang Poon, On-Chip Dynamic Programming Network Using TSV-based 3D Stacking Technology, (Invited paper) SAMOS, 2011

    • 13.Raaed Al-Dujaily, Terrence Mak, Fei Xia, Alex Yakovlev and Maurizio Palesi, Run-Time Deadlock Detection in Networks-on-Chip Using Coupled Transitive Closure Networks, pp 1-6, DATE - Design, Automation and Test in Europe, 2011 (Best Paper Award); EI: 11975122

    • 14.Yu Li, Alex Yakovlev, Terrence Mak, Redressing Timing Issues for Speed-Independent Circuits in Deep Submicron Age, pp 1-6, DATE - Design, Automation and Test in Europe, 2011; EI: 11975254

    • 15.Bo Yu, Terrence Mak, Xiangyu Li, Fei Xia, Alex Yakovlev, Yihe Sun, Reconfigurable Streaming Kernels for Multichannel Neurophysiological Recording Systems, (in Press) DATE - Design, Automation and Test in Europe Workshop on Design Methods and Tools for FPGA-based Acceleration of Scientific Computing, 2011

    • 16.Kin-Fai Tong, Terrence Mak, and Jordan Ivanchev, Micro-Antenna Design for Intra-Cortical Proximity Communication, iWAT, 2011; EI:11962216

    • 17.B. Yu, T. Mak, X. Li, A. Yakovlev, “A Stream-Based Hebbian Eigenfilter for Real-Time Neurophysiological Signal Processing”, Proc. IEEE Biomedical Circuits & Systems Conference, 2010, in Press; EI:11795835

    • 18.K. Lam, T. Mak and C. Poon, “Simulation of large-scale dynamic programming networks on 3D implementation platform”, Proc. of TENCON, 2010, in Press; EI:12307870

    • 19.Bo Yu, Terrence Mak, Xiangyu Li, Fei Xia, Alex Yakovlev, Yihe Sun, “A Reconfigurable Hebbian Eigenfilter for Neurophysiological Spike Train Analysis”, Proc. IEEE International Conference on Field Programmable Technology, 2010, in Press.; EI: 11770314

    • 20.Terrence Mak, P. Y. K. Cheung, K.P. Lam and Wayne Luk, “A DP-Network for Optimal Dynamic Routing in Network-on-Chip”, in Proc. CODES/ISSS, pp 119-128, Grenoble, 2009; EI:

    • 21.Li Wang, Terrence Mak, P. Sedcole and P. Y. K. Cheung, “Throughput Maximization for Wave-Pipelined Interconnects Using Cascaded Buffers and Transistor Sizing”, in Proc. IEEE International Symposium on Circuits and Systems, pp 1293-1296, Taipei, 2009; EI:10760329

    • 22.Terrence Mak, P. Sedcole, P. Y. K. Cheung and W. Luk, “Wave-Pipelined Signalling for On-FPGA Communication”, in Proc. IEEE International Conference on Field Programmable Technology, pp 9-16, Taipei, 2008; EI:10459573

    • 23.Terrence Mak, Pete Sedcole, Peter Y.K. Cheung and Wayne Luk, “Interconnection Lengths and Delays Estimation for Communication Links in FPGAs”, in Proc. ACM International Conference on System Level Interconnect Prediction, pp 1-10, Newcastle, 2008

    • 24.Terrence Mak, Crescenzo D’Alessandro, Pete Sedcole, Peter Y.K. Cheung, Alex Yakovlov and Wayne Luk, “Global Interconnections in FPGAs: Modeling and Performance Analysis”, in Proc. ACM International Conference on System Level Interconnect Prediction, pp 51-58, Newcastle, 2008

    • 25.Terrence Mak, Pete Sedcole, Peter Y.K. Cheung and Wayne Luk, “A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing”, in Proc. ACM/IEEE International Symposium on Networks-on-Chip, pp 173-182, Princeton, 2007; EI:9498396

    • 26.Terrence Mak, Kai-Pui Lam, H.S. Ng, Guy Rachmuth, Chi-Sang Poon, “A Current-Mode Analog Circuit for Reinforcement Learning Problems”, in Proc. International Symposium on Circuits and Systems, pp 1301-1304, New Orleans, 2007; EI:9539209

    • 27.Terrence Mak, Pete Sedcole, Peter Y.K. Cheung and Wayne Luk, “On-FPGA Communication Architectures and Design Factors”, in Proc. Field-Programmable Logics and Applications, pp 1-8, Madrid, 2006; EI: 9605464

    • 28.Terrence Mak, C.-S. Poon, “Temporal-Difference Reinforcement Learning: High-Speed Analog Simulation Using Parallel VLSI Circuits”, in Proc. Society for Neuroscience Symposium, Atlanta, 2006

    • 29.Terrence Mak, G. Racchmuth, K.P. Lam, C.S. Poon, “Field Programmable Gate Array Implementation of Neuronal Ion Channel Dynamics”, in Proc. IEEE International EMBS Conference on Neural Engineering, Arlington, 2005. EI:8521240

    • 30.Terrence Mak and K.P. Lam, “Embedded Computing for Maximum-Likelihood Phylogeny Inference Using Platform FPGA”, in Proc. ACM/IEEE Symposium on Computational Systems Bioinformatics, Palo Alto, 2004 EI:8230308

    • 31.Terrence Mak and K.P. Lam, “FPGA-Based Computation of Maximum-Likelihood Phylogenetic Tree Evaluation”, in Proc. Field-Programmable Logics and Applications, Antwerp, 2004 EI: 8392880

    • 32.H.S. Ng, Terrence Mak and K.P. Lam, “Field Programmable Gate Arrays and Analog Implementation of BRIN for Optimization Problems”, in Proc. International Symposium on Circuits and Systems, Bangkok, 2003; EI: 7762745

    • 33.K.P. Lam and Terrence Mak, “On Computing Transitive-Closure Equivalence Sets Using a Hybrid GA-DP Approach”, in Proc. Field-Programmable Logics and Applications, Montpelier, 2002; EI: 7462589

    • 34.Alex Yakovlev, Terrence Mak, “Apparatus and Method for Voltage Sensing”, UK Patent Application 1005372, March, 2010